With a demand for miniaturizing semiconductor packages, semiconductor chips have been used as very thin films, and bonding wires connected to semiconductor chips have been miniaturized. In addition, since very thin semiconductor chips can be formed, there has been a trend of a three-dimensional packaging technology in which a plurality of semiconductor chips is laminated to provide a multilayer semiconductor chip laminate.
In multilayer semiconductor chip laminates, the mere lamination of semiconductor chips having the same size causes a bonding wire connected to the underlying semiconductor chip to contact the overlying semiconductor chip, likely leading to failure to wire bond these. Then, a method of laminating semiconductor chips having different sizes and a method of forming a clearance between semiconductor chips have been devised. However, it has been not easy to horizontally laminate semiconductor chips without damaging each of the semiconductor chips.
In contrast, there have been conventionally examined a method of protecting wires of a lower semiconductor chip in order to obtain a reliable semiconductor chip laminate, a method of interposing a spacer chip between semiconductor chips so that the semiconductor chips are horizontally laminated, and the like. Patent Document 1, for example, discloses a method of forming spacers in a scattered manner on a face of one semiconductor chip on which the other semiconductor chip is to be laminated, upon laminating a plurality of semiconductor chips, and thereafter laminating the other semiconductor chip. Patent Document 2 discloses a method of laminating dummy chips and spacers between semiconductor chips to be connected, upon laminating a plurality of semiconductor chips.
However, semiconductor packages have recently been more and more miniaturized, and the distance between a semiconductor chip and a wire bonding pad have become shorter and shorter. As a result, novel problems that the methods of Patent Document 1 or Patent Document 2 cannot address have arisen.
That is, conventional adhesives for bonding a semiconductor chip to a substrate or another semiconductor chip extend from the semiconductor chip and reach a wire bonding pad. As the distance between a semiconductor chip and a wire bonding pad becomes shorter, an extended adhesive, that is, what is called a fillet, makes wire bonding difficult. In the case where the amount of the adhesive used is reduced in order to prevent the extension of the adhesive, the adhesive does not wet and spread on the entire bonded surface between the semiconductor chip and the substrate or another semiconductor chip, and causes a cavity after mold sealing, resulting in difficulty in achieving sufficient reliability of the produced semiconductor chip laminate.